1. Field of the Invention
The present invention relates to the field of computers and computer systems. More specifically, the present invention relates to power reduction in integrated Static Random Access Memories (SRAMs) used as a cache tag array.
2. Description of Related Art
A microcomputer system generally comprises a microprocessor, a memory subsystem, a bus and other peripherals. The microprocessor executes instructions and the memory subsystem stores data and instructions for the microprocessor. The bus serves as a communication pathway between the microprocessor and other devices in the computer system.
The memory subsystem typically comprises some slow and inexpensive memory such as Dynamic Random Access Memory (DRAM) and fast and expensive memory such as SRAMs. While many personal computer system memories have gotten taster over the years, the increase in the speed of system memory comprised of Dynamic Random Access Memory (DRAM) has not kept pace with the increase in microprocessor speeds.
To maximize system performance, microprocessor system designers are incorporating cache memories into the system memory configurations. Cache memories are very fast local memories usually made up of fast and expensive Static Random Access Memory (SRAM). Cache memories are used for temporarily storing copies of data and instructions used by the microprocessor. The microprocessor can retrieve a copy of data from the cache memory faster than from the slow main system memory (e.g., DRAMs) because the access times of the main system memory are longer. Therefore, the use of cache memories can significantly improve the performance of the computer system by circumventing the long access time to the main system memory in favor of the short access times of the cache memories.
Computer systems often include a memory controller to coordinate memory accesses. Some prior art systems use a tag SRAM array as a part of a memory controller. The tag SRAM functions as a look-up table to addresses stored therein which correspond to each separate data address in memory. Each address is stored in a separate entry, referred to as a tag. In this way, the tag SRAM identifies the data that is currently stored in a cache memory. When the microprocessor requests information from main memory, the memory request is initially sent to a cache memory. As information is copied into the cache memory, its main memory address is stored in the tag SRAM. The tag SRAM does not only hold the original main system memory addresses of code and data stored in the cache memory, but also additional status bits used by a cache management logic to determine when the tag SRAM is being accessed. The cache management logic takes a memory request from the microprocessor and compares it with an entry in the tag SRAM. When the memory request address matches an address stored in the tag SRAM, the cache memory returns the information requested by the microprocessor. If the memory request address does not match any entry in the tag SRAM, the memory request is passed on to main memory.
Storing cache memory data addresses in the tag SRAM requires circuitry in the tag SRAM to be on during most of the computer system up-time to enable data to be read from and written to the tag SRAM. Having the tag SRAM on all the time presents some problems. One of these problems is that because of its high performance nature, the tag SRAM consumes a lot of power and dissipates a lot of heat. The high heat dissipation of the tag SRAM makes it difficult to package it in low cost packages like plastic. The high power consumption of the tag SRAM also contributes to an increase in the overall system power consumption which adversely affects the overall system performance of many prior art computer systems.
To handle the power consumption by the tag SRAM and other components, many prior art systems use bigger power supplies, better cooling mechanisms, and more system board space to accommodate these components in order not to degrade the overall system performance.
In an effort to increase system performance by reducing the heat generated by the tag SRAM, prior art system designers also package the tag SRAM in ceramics. Although ceramic packaging helps dissipate heat generated by prior art systems, it can be very expensive and it does not solve the power consumption problem of the tag SRAM.
To reduce the power consumption by the tag SRAM and the extra cost associated with using such memories in computer systems, a method and apparatus for incorporating the high performance of a cache memory with the low packaging cost of DRAM memory is needed. The present invention provides a method and apparatus for reducing power consumption of a tag SRAM used with cache memories or in memory controllers, so that the amount of heat dissipated can be reduced without impacting the performance of the tag SRAM. The present invention also provides a memory controller that combines the high performance of an integrated tag SRAM with a low cost packaging of DRAMs.